1. Field of the Invention
Generally, the present disclosure relates to the field of integrated circuits, and, more particularly, to field effect transistors and manufacturing techniques on the basis of stressed dielectric layers formed above the transistors used for generating a different type of strain in channel regions of different transistor types.
2. Description of the Related Art
Integrated circuits are typically comprised of a large number of circuit elements located on a given chip area according to a specified circuit layout, wherein, in complex circuits, the field effect transistor represents one predominant circuit element. Generally, a plurality of process technologies for advanced semiconductor devices are currently practiced, wherein, for complex circuitry based on field effect transistors, such as microprocessors, storage chips and the like, CMOS technology is currently one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using CMOS technology, millions of complementary transistors, i.e., N-channel transistors and P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A field effect transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, comprises so-called PN junctions that are formed by an interface of highly doped drain and source regions with an inversely or weakly doped channel region disposed between the drain region and the source region. The conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed above the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on the dopant concentration, the mobility of the majority charge carriers and, for a given extension of the channel region in the transistor width direction, on the distance between the source and drain regions, which is also referred to as channel length. Hence, in combination with the capability of rapidly creating a conductive channel below the insulating layer upon application of the control voltage to the gate electrode, the conductivity of the channel region substantially determines the performance of MOS transistors. Thus, the reduction of the channel length, and associated therewith the reduction of the channel resistivity, may be a dominant design criterion for accomplishing an increase in the operating speed of the integrated circuits.
The shrinkage of the transistor dimensions, however, involves a plurality of issues associated therewith that have to be addressed so as to not unduly offset the advantages obtained by steadily decreasing the channel length of MOS transistors. One issue associated with reduced gate lengths is the occurrence of so-called short channel effects, which may result in a reduced controllability of the channel conductivity. Short channel effects may be countered by certain design techniques, some of which, however, may be accompanied by a reduction of the channel conductivity, thereby partially offsetting the advantages obtained by the reduction of critical dimensions.
In view of this situation, it has been proposed to enhance device performance of the transistor elements not only by reducing the transistor dimensions but also by increasing the charge carrier mobility in the channel region for a given channel length, thereby increasing the drive current capability and thus transistor performance. For example, the lattice structure in the channel region may be modified, for instance, by creating tensile or compressive strain therein, which results in a modified mobility for electrons and holes, respectively. For example, creating tensile strain in the channel region of a silicon layer having a standard crystallographic configuration may increase the mobility of electrons, which in turn may directly translate into a corresponding increase of the conductivity of N-type transistors. On the other hand, compressive strain in the channel region may increase the mobility of holes, thereby providing the potential for enhancing the performance of P-type transistors.
One efficient approach in this respect is a technique that enables the creation of desired stress conditions within the channel region of different transistor elements by adjusting the stress characteristics of a dielectric layer stack that is formed above the basic transistor structure. The dielectric layer stack typically comprises one or more dielectric layers which may be located close to the transistor and which may also be used in controlling a respective etch process in order to form contact openings to the gate and drain and source terminals. Therefore, an effective control of mechanical stress in the channel regions, i.e., effective stress engineering, may be accomplished by individually adjusting the internal stress of these layers, which may also be referred to as contact etch stop layers, and by positioning a contact etch stop layer having an internal compressive stress above a P-channel transistor while positioning a contact etch stop layer having an internal tensile strain above an N-channel transistor, thereby creating compressive and tensile strain, respectively, in the respective channel regions.
Typically, the contact etch stop layer is formed by plasma enhanced chemical vapor deposition (PECVD) processes above the transistor, i.e., above the gate structure and the drain and source regions, wherein, for instance, silicon nitride may be used due to its high etch selectivity with respect to silicon dioxide, which is a well-established interlayer dielectric material. Furthermore, PECVD silicon nitride may be deposited with a high intrinsic stress, for example, up to 3 Giga Pascal (GPa) or higher of compressive stress and up to 2 GPa and higher of tensile stress, wherein the type and the magnitude of the intrinsic stress may be efficiently adjusted by selecting appropriate deposition parameters. For example, ion bombardment, deposition pressure, substrate temperature, gas flow rates and the like represent respective parameters that may be used for obtaining the desired intrinsic stress.
During the formation of the two types of stressed layers, conventional techniques may suffer from reduced efficiency when device dimensions are increasingly scaled by using the 45 nm technology and even further advanced approaches, due to the limited conformal deposition capabilities of the deposition processes involved, which may result in respective process non-uniformities during subsequent process steps for patterning the stressed layer and forming contact openings, unless the thickness of the stress-inducing layers is significantly reduced, as will be explained in more detail with reference to FIGS. 1a-1d. 
FIG. 1a schematically illustrates a cross-sectional view of a semiconductor device 100 in an advanced manufacturing stage. As illustrated, the semiconductor device 100 may comprise a substrate 101, which may represent any appropriate carrier material for forming thereabove circuit elements, such as transistors, capacitors and the like. In the example shown, the substrate 101 may comprise a buried insulating layer 102, such as a silicon dioxide layer, on which is formed a semiconductor layer 103, such as a silicon-based layer, which may also include other components such as germanium, carbon and the like. An isolation structure 104, for instance comprised of silicon dioxide, silicon nitride and the like, may be provided within the semiconductor layer 103, thereby defining a first device region 150N and a second device region 150P. The device regions 150N, 150P may comprise a plurality of transistor elements 120, which may have a lateral distance according to the design rules of the technology under consideration. The transistors 120 provided in the first and second device regions 150N, 150P may comprise gate electrode structures 121 including a gate electrode material 121A, frequently comprised of polysilicon, in combination with a metal silicide 121B for enhancing the overall conductivity of the gate electrode structure 121. Moreover, the structure 121 may comprise a gate insulation layer 121C, which separates the gate electrode material 121A from a channel region 122, which in turn is laterally enclosed by drain and source regions 123. Moreover, metal silicide regions 123A may also be formed in the drain and source regions 123, depending on the overall device requirements. It should be appreciated that the transistors 120 are illustrated so as to have substantially the same configuration in the first and second device regions 150N, 150P, wherein, however, the transistors 120 may at least differ in their conductivity type. That is, in the region 150N, a plurality of N-channel transistors 120 may be provided in which the drain and source regions 123 may be heavily N-doped, while, in the device region 150P, P-channel transistors may be provided in which the corresponding drain and source regions 123 may be P-doped. Consequently, as explained above, performance of the transistors 120 in the device region 150N may be enhanced by providing a tensile strain along the channel length direction, i.e., in FIG. 1a the horizontal direction, thereby enhancing electron mobility in the channel region 122. On the other hand, performance of the transistors 120 in the device region 150P may be enhanced by inducing a compressive strain in the channel regions 122 along the channel length direction, as previously explained, in order to enhance hole mobility. For this purpose, a dual stressed liner approach may be used in which a dielectric layer 110 may be formed above the transistors 120 in the device region 150N, which may exhibit a high internal tensile stress level. Similarly, in the device region 150P, a dielectric material 130 may be formed above the transistors 120, which may exhibit a high internal compressive stress level. Moreover, an etch stop layer 111 may be formed at least below the tensile stressed dielectric material 110 and possibly below the compressively stressed dielectric material 130, for instance in the form of a silicon dioxide material and the like. Moreover, a further etch stop layer or etch indicator layer 112 may be formed on the tensile stressed dielectric material 110.
The semiconductor device 100 as illustrated in FIG. 1a may be formed on the basis of well-established conventional process techniques. That is, after providing the basic transistor structures 120, which may involve manufacturing techniques for forming the isolation structures 104, followed by the patterning of the gate electrode structures 121 and the subsequent formation of the drain and source regions 123, typically on the basis of a sidewall spacer structure of the gate electrode structure 121, with subsequent anneal cycles to activate the dopant species and cure implantation-induced lattice damage. Thereafter, the metal silicide regions 123A, 121B may be formed, for instance on the basis of a common silicidation sequence, as is well known in the art. Next, the etch stop layer 111 may be deposited, for instance by PECVD or thermally activated chemical vapor deposition (CVD), depending on the overall process strategy. The etch stop layer 111 may be provided with a sufficient thickness in order to reliably stop an etch process in a later manufacturing stage when an unwanted material of the tensile stressed dielectric material 110 is to be removed from above the device region 150P. Consequently, for a given material composition of the etch stop layer 111, a specific minimum thickness may have to be applied, for instance in the range of 10-30 or more nm, in order to provide the desired etch stop capabilities. Thereafter, in the example shown, the tensile stressed dielectric material 110 may be deposited on the basis of PECVD techniques, in which deposition parameters may be appropriately adjusted so as to deposit a silicon nitride material with a high internal tensile stress level, as is also previously explained. For this purpose, appropriate deposition parameters, such as the degree of ion bombardment during the deposition, the pressure, the substrate temperature, the gas flow rates and the like, may be appropriately adjusted in order to obtain the desired stress level. As previously explained, in sophisticated semiconductor devices, the lateral distance between neighboring gate electrode structures 121 may require a specific adaptation of the thickness of the layer 110 in order to avoid deposition-related irregularities, such as voids, and provide an appropriate surface topography for subsequent process steps, for instance for forming the compressively stressed dielectric material 130 and removing an unwanted portion thereof. On the other hand, the strain level obtained in the channel regions 122 may be substantially determined by the internal stress level of the dielectric materials 110, 130, the amount of stressed dielectric material positioned closely to the channel regions 122 and the presence of any intermediate substantially non-stressed materials, such as the etch stop layer 111. Consequently, the selected thickness for the dielectric material 110 may represent a compromise between an increased amount of highly stressed dielectric material and the suppression of any process non-uniformities.
After the deposition of the tensile stress layer 110, the etch stop or etch indicator layer 112 may be formed, for instance by deposition of silicon dioxide material and the like, wherein a certain layer thickness for a given material composition may have to be used in order to obtain the required etch stop capabilities during a subsequent etch process. For example, the layer 112 may be provided with a thickness of 10 to several tenths of nm, depending on the overall process strategy. Thus, the deposition of the layers 111, 110 and 112 may have to be carried out such that the finally obtained surface topography may still be appropriate for the subsequent deposition and patterning of the dielectric material 130. After the deposition of the etch stop or indicator layer 112, a mask layer, such as a resist layer, may be formed on the basis of sophisticated lithography techniques in order to mask the device region 150N, while exposing the region 150P to an appropriately designed etch ambient in order to remove the exposed portion of the layer 112, followed by the removal of the layer 110, wherein the etch stop layer 111 may be used as a reliable etch stop material. Thereafter, the resist mask may be removed and the compressively stressed dielectric material 130 may be deposited on the basis of well-established PECVD techniques, wherein, in this case, the deposition parameters may be selected such that the desired high compressive stress level may be obtained. Also in this case, respective process parameters, in particular the degree of ion bombardment during the deposition, may be appropriately adjusted. Thereafter, a further lithography process may be performed to add a resist mask for covering the device region 150P while exposing the region 150N. Next, a further etch process may be performed in order to remove the exposed portion of the material 130 while using the layer 112 as an etch stop material. Thereafter, the resist mask may be removed and the further processing may be continued, for instance, by depositing an interlayer dielectric material, such as silicon dioxide, by using well-established process techniques, such as sub-atmospheric CVD (SACVD), high density plasma assisted CVD and the like. Thereafter, the resulting surface topography may be planarized and contact openings may be formed in the interlayer dielectric material wherein the dielectric materials 110 and 130 may act as etch stop layers, which may subsequently be opened on the basis of respective well-established process techniques. Next, the contact openings may be filled with an appropriate material, such as tungsten and the like, in order to provide electrical contact to the drain and source regions 123 and the gate electrode structures 121.
Consequently, on the basis of the highly stressed dielectric materials 110, 130, the tensile stress level and the compressive stress level, respectively, may provide respective strain components in the channel regions 122, thereby enhancing overall performance of the transistors in the regions 150N, 150P. A corresponding process sequence for forming the differently stressed dielectric materials 110, 130 may be referred to as a dual stress liner approach, which, however, may suffer from a reduced efficiency, in particular when device dimensions of the transistors 120 may further be scaled, as will be described later on in more detail.
FIG. 1b schematically illustrates a top view of one of the transistors 120 of the region 150N and the region 150P in order to demonstrate the effect of various strain components in view of the overall transistor performance. As illustrated, in an N-channel transistor, indicated as 120N, a tension along the transistor length direction, as indicated by the arrow L, may provide enhanced electron mobility. Similarly, a tension along the transistor width direction, indicated by arrow W, may also contribute to enhanced transistor performance. On the other hand, in a P-channel transistor, indicated as 120P, a compressive strain along the transistor length direction may result in enhanced hole mobility, while a tension along the transistor width direction may also be advantageous with respect to enhanced hole mobility. Consequently, due to the mechanism as described with reference to FIG. 1b, the dielectric material 110 having the internal tensile stress level may provide a substantially unidirectional tensile strain along the length direction, while, on the other hand, the highly compressively stressed dielectric material 130 may provide a substantially unidirectional compressive strain component along the transistor length direction. However, the corresponding strain-inducing mechanism may significantly depend on the overall device dimensions, as will be explained with reference to FIGS. 1c-1d. 
FIG. 1c schematically illustrates a cross-sectional view of a portion of the semiconductor device 100, for instance the device region 150N may be illustrated. In the example shown, it may be assumed that a distance 124 between the neighboring transistors 120, i.e., the respective gate electrode structures 121, may be approximately 200 nm and significantly greater, wherein also the gate length may be 50 nm and greater. In this case, a thickness 110T of the dielectric material 110 may be appropriately selected to provide the desired surface topography while also respecting the gap filling capabilities of the corresponding deposition technique, as previously explained. On the other hand, a thickness 111T of the etch stop layer 111 and a thickness 112T of the layer 112 may be substantially determined by the required etch stop capabilities, substantially without depending on the overall device geometry. In this case, the fraction of highly stressed dielectric material positioned in close proximity to the transistors 120 is substantially determined by the corresponding ratio of the thickness 110T on the one hand and the combined thickness 111T and 112T on the other hand.
FIG. 1d schematically illustrates the situation for a highly sophisticated semiconductor device in which the distance 124 may be reduced due to a scaling of the overall device dimensions and may be approximately 100 nm and even less. Since the thickness 111T and the thickness 112T may be substantially independent from the overall device dimensions, as previously explained, the thickness 110T of the stress-inducing layer 110 may have to be reduced over-proportionally in order to provide a required surface topography for the further processing of the device 100, such as, for example, providing the material 130 and patterning the same, as illustrated in FIG. 1a and described above. Consequently, the amount of material provided by the etch stop layers 111 and 112 may represent a moderately high fraction of the entire amount of material positioned in close proximity to the basic transistor structures 120, and hence the degree of performance gain based on the dual stress liner approach may be reduced with further device scaling.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.